TSV BIST, entails a combination of innovative techniques for improved verification of the quality and reliability of 2.5/3D IC packaging and for prognostics so that related interconnect operational faults can be determined before actual failure occurs.
This technology is the first to address the difficult issue of 2.5/3D IC package interconnect integrity after assembly is done and when the related devices are deployed in larger systems. The innovation will improve reliability of TSV-based packaging and provide prognostics so that interconnect-related operational faults can be determined before actual system failure occurs.
- Sensor: SJ BIST/SMRT Connector/TSV BIST
- Data Type: Pin Read/Write
- Reasoner: SJ Algorithm
- GUI: Sentinel Dashboard
2.5D ICs and 3D ICs are advanced packaging methodologies based on stacks of ICs that incorporate through-silicon vias (TSVs) for chip-to-chip communication: 2.5D ICs use an interposer to route the signals among the stacked chips, and 3D ICs use the TSVs to directly connect between the chips without the aid of an interposer. While the potential benefits of increased circuit density and performance are alluring, one of the hurdles the electronics industry must face is how to ensure the reliability of such components. These dense packages are created with new manufacturing technologies and must deal with a great deal of heat in a very small space and, without a long track record of field data to rely upon, it is difficult to project how well they will endure years into the future. This issue is magnified because some of the applications that could most benefit from 2.5D/3D IC technology – e.g., satellites, telecommunications, and transportation systems – are also among the most demanding when it comes to safety and reliability.
Ridgetop Group has developed a technology suite called TSV BIST™ which is the first to address this thorny problem. TSV BIST (BIST is an acronym for built-in self-test) consists of tiny monitors that are embedded into the 2.5D IC and 3D IC chip stacks that can detect degradation in the chip-to-chip interconnections, identify intermittencies, and ultimately warn of impending interconnect failure – before the failure actually occurs. TSV BIST incorporates and builds upon proven Ridgetop technology for board-to-package interconnection monitoring (SJ BIST™) and power and ground signal monitoring (Q-Star PG Mon™).
Features & Benefits
- Ridgetop’s TSV BIST test methods are smaller and better electronic products with more reliable operation, yielding less waste and customer returns, higher system uptimes and lower system downtimes, and more efficient problem diagnosis, all contributing to more energy-efficient applications and a greener world.
- A rule of thumb is that the cost to fix a problem grows by a factor of 10 for each successive stage of an entity’s life cycle. The 2.5/3D ICs go through manufacturing, packaging, assembly, and deployment stages. A finished system that fails because of an unreliable TSV can lead to the loss of millions of dollars, but failures at even earlier stages can be quite expensive to detect, diagnose, isolate, and repair.
- TSV BIST can be applied to 2.5/3D ICs at each of these stages and can result in tremendous savings for agencies and companies.
- The cost to implement this technology – adding a small amount of circuitry to each 2.5/3D IC – is insignificant when compared with the potential losses if this technology is not deployed.
DigIO: A Power-Draw Anomaly Detection Method
Inline Image Ridgetop’s DigIO™ (Digital Input/Output) product provides an innovative method for non-intrusively assessing the state of health (SoH) and remaining useful life (RUL) of complex digital electronic systems including CPU control boards. DigIO is a valuable tool for reducing maintenance costs and increasing operational readiness of digital-based systems. It has the potential to provide complex electronic modules with an advanced level of critical-component and system-SoH visibility with the real-time knowledge of components’ RUL.
The ability to detect impending failures in complex electronic systems supports condition-based maintenance (CBM) programs to reduce maintenance costs and increase operational readiness of advanced systems such as industrial internet communication links with factory floor robotic cells and other systems. The DigIO technology also has significant value for commercial applications including navigation and communications equipment (air, land, sea and space), digital processing, microprocessors (FPGAs), microcontrollers (MCUs), and computers.
DigIO employs an advanced correlation algorithm using a correlation method to detect anomalous conditions in the monitored asset. Basically, DigIO correlates the input bitstream to the digital products on the power bus of a digital-based system. If the digital system is operating within its specifications, there will be a high correlation between the input pseudorandom sequence (PRS) and the power supply noise; but if the digital system is degraded, the degree of correlation is reduced, with the degree of non-correlation increasing as degradation increases. The amount of degradation can be mapped in a fault-to-failure progression (FFP) model compatible with other Ridgetop analysis modules.
The DigIO utility leverages key technology parameters such as non-invasiveness, Weibull distribution data capture, intermittency detection, and most importantly, real-time system-level health visibility.
Today’s operators in the commercial aerospace market are plagued by ever-increasing operating and maintenance costs while facing tighter safety restrictions by the FAA. DigIO can be used as a dynamic utility for aircraft maintenance personnel to constantly monitor the RUL of critical aircraft components accurately and non-invasively, thus eliminating the need for the tedious line and system inspections which are performed routinely.