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ANALOG-TO-DIGITAL


Category: InstaCell™

Ridgetop has the technical experience and proven results for critical aerospace, automotive, and semiconductor sectors. Our ADC IP library includes:
Rad-hard ADCs for aerospace and military applications
Non-rad-hard ADCs for commercial applications

Foundries/Processes& Geometries

Foundries
Ridgetop maintains a staff of fully trained specialists with expertise in different foundries:

  • TSMC
  • IBM
  • X FAB
  • ON Semi
 

Processes & Geometries
Ridgetop’s ADC technology capabilities extend across several processes and geometries. Ridgetop strives to meet customers’ needs. Our technology is designed to be flexible for customized designs made to order. Some of the processes and geometries provided by Ridgetop include:

  • CMOS 130 nm, 180 nm, 250 nm, 350 nm, 600 nm
  • SiGe BiCMOS 130 nm

12-Bit, 40MSps

Rad-Hard Adjustable Sample Rate ADC, 12-bit, Ultra-Low Power

Features and Benefits:

  • Pipeline architecture
  • 40 MSPS sampling speed
  • 12 bits resolution (10 bits ENOB)
  • Rad-hard to >3.5 Mrad TID
  • Rad-hard to >120 MeV-cm2/mg SEL
  • Low power, 22.5 mW
  • Thin-oxide 130 nm SiGe
  • IBM 8HP high performance fabrication process
  • Input analog bandwidth 50 MHz
  • INL <1.5 LSB, DNL <0.95 LSB
  • Sleep mode reduces power to 9 mW
 

General Description
This innovative analog-to-digital data converter (ADC) combines high resolution, high sampling speed, and low power, and it is designed for high levels of radiation hardness. The ADC is hard to total ionizing dose (TID) of up to 3.5 Mrad(Si), and is immune to single-event latchup (SEL) and single-event functional interrupt (SEFI). Latency is below 100 ns, and power dissipation is 22.5 mW.
Ridgetop achieved high radiation hardness and performance levels using the IBM 8HP SiGe process.
The die is 4.6 x 4.6 mm, in a 48-pin QFN package. The pin-programmable sleep mode reduces power to 9 mW when idle.

12-bit Ultra-Low Power

10-Bit, 4MSps

ADC 10-bit, 4 MS/s, TSMC 0.25 µm IP Core

Features and Benefits:

  • 10 bits of resolution
  • 4 MS/s sampling rate
  • TSMC 0.25 μm mixed-signal process (retargetable)
  • 3.0 to 3.6 V analog supply voltage
  • 2.25 to 2.75 V digital supply voltage
  • Area 1.25 x 1.5 mm (TSMC 0.25 μm process)
  • Pin provided for enable mode
  • External (or internal) reference voltage
  • Up to 10 analog inputs
  • MIM capacitors
  • Pipeline architecture
  • Includes complimentary license of patented PDKChek® die-level process monitor yield improvement solution
 

General Description
Ridgetop Group’s 10-bit, 4 MS/s ADC core utilizes a pipeline architecture in the TSMC 0.25 μm process. The ADC converter design is 10-bit 4 MS/s.
The cell incorporates a 10-bit pipeline analog-to-digital converter with up to five sample-hold blocks Four sample-hold blocks are used in parallel to sample input voltage and current. The fifth sample-hold block is used with the input multiplexer to provide up to eight auxiliary inputs. The cell also includes a current-to-voltage converter that converts current input signals to voltages.

ADC design block diagram

14-Bit, 40MSps

14-bit ADC/VGA, 40 MS/s, TSMC 180 nm IP Core

Features and Benefits:

  • 14 bits of resolution
  • 40 MSPS sampling rate
  • TSMC 180 nm mixed-mode process
  • 3.3 V analog supply voltage
  • 3.3 V digital I/O supply voltage
  • Differential input
  • Pipeline architecture
  • 4-bit variable gain
  • Includes complimentary license of patented PDKChek® die-level process monitor yield improvement solution
 

General Description
Ridgetop’s silicon-proven ADC is optimized for high performance imaging applications and other high data rate, high SNR applications. This ADC is designed for the TSMC 180 nm mixed-mode process using MIM capacitors. The ADC has fully differential variable gain input, and has pipeline architecture with 1.5 bits-per-stage resolution, with digital error correction. Each stage makes two conversions per clock cycle, resulting in a 2-bit output. The architecture allows individual ADC stages to be scaled and optimized for both noise and power.

ADC pipeline design

14-Bit, 40MSps

14-bit Adc, 40 MSpS, tSMc 180 nm ip core

Features and Benefits:

  • 14 bits of resolution
  • 40 MSPS sampling rate
  • TSMC 180 nm mixed-mode process
  • 3.3 V analog supply voltage
  • 3.3 V digital I/O supply voltage
  • Differential input 
  • Pipeline architecture
  • 4-bit variable gain
  • Includes complimentary license of patented pdKchek® die-level process monitor yield improvement solution
 

General Description:
Ridgetop’s silicon-proven ADC is optimized for high-performance imaging applications and other high data rate, high SNR applications. This ADC is designed for the TSMC 180 nm mixed-mode process using MIM capacitors. The ADC has fully differential variable gain input, and has pipeline architecture with 1.5 bits-per-stage resolution, with digital error correction. Each stage makes two conversions per clock cycle resulting in a 2-bit output. The architecture allows individual ADC stages to be scaled and optimized for both noise and power.

ADC pipeline design - seven MDAC stages 1.5 bits per stage

12-Bit, 650MSps, Rad-Hard SIGE

12-bit, 650 MS/s, Rad-Hard SiGe ADC, IBM 130 nm IP Core

Features and Benefits:

  • 12 bits of resolution (11-bit ENOB)
  • 650 MS/s sampling rate
  • IBM 8HP 130 nm SiGe process
  • 1.5 GHz analog bandwidth
  • 650 mW power
  • Hard to 300 krads (Si) of TID
  • Hard to 120 MeV-cm2/mg of SEL
  • 2.5 V, 4.5 V analog supply voltage
  • 1.2 V digital I/O supply voltage
  • Input range 2 V
  • Pipeline architecture

General Description:
Ridgetop’s rad-hard pipeline ADC is optimized for high performance applications that require very high input analog bandwidth and low power consumption, including spaceborne applications. This ADC is designed in the IBM 8HP silicon-germanium BICMOS process. The ADC has a full-speed, front-end sample-and-hold amplifier (SHA) that can accept input analog bandwidth to 1.5 GHz.
The ADC structure shown in Figure 1 is a 2-channel time-interleaved pipeline ADC with an input SHA. The sampling frequency of the SHA can be as low as 650 MHz to under-sample the input IF-signal of 1.5 GHz. After the IF signal is sampled with the SHA, two channels of pipeline ADCs digitize the base-band signal. The sample rate of each channel is half of the sample rate of the SHA.
Each pipeline channel consists of one 2.5-bit stage, eight 1.5-bit stages, and a 3-bit flash ADC at the end, which are available as building blocks for other ADCs. The sub-blocks include bandgap reference (BGR), three separate operational transconductance ampliers (OTAs), comparators, the ADC pipeline stages, and the SHA.

Time-interleaved pipeline ADC architecture